Logic circuits are commonly used to provide control signals for memories (e.g., memory arrays). In some implementations, a logic circuit includes P-type Metal-Oxide Silicon (PMOS) transistors in the current keeper circuit (e.g., the current keeper) and N-type MOS (NMOS) transistors in the memory cells. In various situations, both the active current leakage and passive current leakage in the memory cells cause stress and/or failures to the PMOS transistors in the current keeper in different types of memory designs, including, for example, read-only memory (ROM), static random access memory (SRAM), etc. The variations in manufacturing process, voltage, and temperature (e.g., PVT variations) worsen the stress/failures. Process variations result in different driving capabilities of transistors causing a transistor to be slower or faster than another transistor, especially for different transistor types (e.g., P-type, N-type). Generally, the failures occur at low operation voltages (e.g., VCC) and when one type of transistor is slower than the other type. In one approach, when reading a “1” (e.g., a high, a high logic level), the stronger keeper current from the PMOS transistors disturbs the circuit's evaluation operation when the ratio I_active_leak/Ikeeper approaches 1 where I_active_leak is the leakage/flow when the circuit is in an active current leakage condition. In this situation, extending the pulse width of the corresponding word line (e.g., WL) does not cure the problem. For another example, reading a “0” (e.g., a low, a low logic level) fails when the ratio Ikeeper/I_passive_leak is small, where I_passive_leak is the leakage current when the circuit is in a passive current leakage condition. Some approaches, to cure the above problems, increase the size of the transistors forming the keeper current. This solution, however, increases the propagation delay from the input to the output of the current keeper causing slow access time (e.g., speed) and circuit operation variations. Some approaches add controls pins with user capabilities to select the appropriate pins to have the corresponding current flows and thus the appropriate keeper current, but also add complexity to the circuit.
Like reference symbols in the various drawings indicate like elements.